The present invention relates to an expandable slave device system in a computer system, and in particular to an expandable slave device system using a global bus and multiple subsystem buses.
The size of computer application programs is ever-increasing; therefore, the amount of memory needed to handle the application programs is also increasing. To reduce the execution time of the application programs, larger amounts of memory, such as semi-conductor random access memory (RAM) are added to computer systems.
In FIG. 1, a bus system is a chip-to-chip electronic communications system that connects one or more slave devices 42 to a master device 44 through shared communication lines 46, called a bus. Typically, the slave devices 42 are memory devices. In a typical memory system 50, the bus 46 interconnects a memory control master device (M) 44 and memory devices (D) 42. The bus 46 is a bi-directional data bus having many signal lines 54-1 to 54-m. In a bidirectional data bus, the memory control master device 44 transmits information on the signal lines 54 to the memory devices 42, and the memory devices transmit information back to the memory control master device 44 on the signal lines 54. The data bus 46 has a loaded bus impedance of ZL. For reliable operation at the loaded bus impedance ZL at a given frequency, the memory system 50 has a maximum predetermined number (from one to N) of memory devices 42 connected to the data bus 52. The bi-directional data bus 46 has many bus signal lines 54. One end of each bus signal line 54 terminates at an I/O pin 56-M on the master device 44; the other end of each bus signal line terminates at a resistive terminator (T) 60. The impedance or resistance of the resistive terminator 60 matches the loaded bus impedance ZL to minimize reflections by absorbing signals transmitted on the bus signal line 54. The opposite end of each terminator 60 connects to a termination voltage VT which provides an AC ground and sets the DC termination voltage of the bus signal line 54. Because the voltage of the bus signal lines 54 is pulled-up to the value of the termination voltage VT, the termination voltage VT represents a state of a logical data signal, such as a logical zero, for digital signals transmitted on the bus signal lines 58. Another state of the logical data signal, such as a logical one, is represented by a voltage that is proportional to an amount of current that flows through the resistive terminator 60.
Each signal line connects to a write buffer 62 and a read buffer 63 in the master device 44. The read buffer 63 receives data signals from its respective signal line. The write buffer 62 has a drive circuit that drives data signals onto its respective signal line of the bus 46.
When driving a logical one, the drive circuit of the write buffer 62 causes current to flow through the resistive terminator 60. Switched current sources, such as open drain NMOS devices, can be used as drive circuits in either the master device 44 and the memory devices 42. The drive circuit generates a logical zero state by not providing a path for current to flow through the resistive terminator T 60 to ground. The drive circuit generates a logical one state by providing a path for current to flow through the resistive terminator 60 to ground. In a binary system, a logical zero is represented by the termination voltage VT, which will also be referred to as VHi; and, a logical one is represented by a low voltage VLo in accordance with relationship one as follows:
VLo=(VTxe2x88x92IoZL).xe2x80x83xe2x80x83(1)
The current Io is the nominal amount of current sunk by an active drive circuit when driving a logical one.
This signaling scheme has two benefits. First, the drive circuit does not consume power when driving one of the logical statesxe2x80x94the logical zero state VHi. Second, the drive circuit provides a high output impedance to the bus signal lines 54, which minimizes the amount of energy lost as the signals propagate, past the memory devices 42, towards the resistive terminator 60 at the ends of the data bus 46. At the master device 44, the input impedance is equal to the full loaded impedance ZL of the bus signal line 54. When transmitting signals, the master device 44 generates full-swing signals having a voltage difference VSwing equal to the difference between the voltages representing the logical zero and logical one states in accordance with relationship two as follows:
Vswing=(VHixe2x88x92VLo).xe2x80x83xe2x80x83(2)
The signals transmitted by the master device 44 propagate down the bus signal line 54, past the memory devices 42, and terminate at the resistive terminator 60. The conductor between the bus signal line 54 and an I/O pin 56 of the memory device 42 is referred to as a stub. As long as the I/O pins 56-D of the memory devices 42 form short stubs and present a high input impedance, the signals lose little energy and produce minimal parasitic reflections as the signals travel down the bus signal line. Stubs are considered to be short if their electrical lengths are shorter than the rise and/or fall times of the signals. The electrical length refers to the amount of time for a signal to propagate from one end of the stub to the other. The physical length of the stub is directly proportional to the electrical length of the stub.
When a memory device 42 transmits to the master device 44, although connected to a single bus signal line 54, each drive circuit in the memory device 42 effectively xe2x80x9cseesxe2x80x9d two linesxe2x80x94one line towards the master 44 and one line towards the resistive terminator 60. Each line has a net impedance equal to one-half of the full loaded impedance ZL of the bus signal lines 54 (xc2xdZL). Assuming that the drive circuits in the memory devices 42 also sink an amount of current equal to Io, the signals that emerge from the memory device I/O pins 56-D split at the bus signal line 54 with half the signal voltage traveling toward the master 102 and half toward the resistive terminators 60. The half-swing signals that travel toward the resistive terminators 60 pass by the other memory devices 42 and are absorbed by the resistive terminators 60. The half-swing signals that travel toward the master device 44 pass by other memory devices 42 and encounter an open circuit at the end of the bus signal line 54 at the master device I/O pin 56-M. The open circuit causes the signals from the memory device 42 to reflect back down the bus signal lines 54 towards the resistive terminator 60 which doubles the voltage at the I/O pin of the master device 56-M. Although only half of the voltage (i.e. xc2xdVSwing) was transmitted towards the master device 44, the master device 44 still receives a full swing signal VSwing at its I/O pins 56-M because of the reflection, provided that the bus signal lines 54 terminate in a high impedance (i.e., an open circuit) at the master device 44. The other memory devices 42 in the memory system 50 will see half-amplitude signals pass their I/O pins 56-D at each of two different times. As a result, these half-amplitude signals cannot be reliably detected by the other memory devices 42. Since a memory device 42 transmits data to the master device 44 and not to another memory device 42, this result is acceptable. Regardless of which memory device 42 in the memory system 50 is transmitting, a full swing signal VSwing appears at the input of the intended receiving device.
FIG. 2 shows a diagram of the structure and electrical properties of an exemplary bus signal line 54 of the prior art memory system 50 of FIG. 1. The portion of the bus signal line 54 that connects to the memory devices 42 forms a repetitive structure of signal line segments 64 and memory devices 42 as shown. Each signal line segment 64 can be modeled as a transmission line of length d having an inductance per unit length of Lo, a capacitance per unit length of Co, a dielectric conductance per unit length of Gp, and a conductor resistance per unit length of Rs. The lossy, complex characteristic impedance of such a transmission line is in accordance with relationship three as follows:                               Z          OL                =                                                            Rs                +                                  j                  ⁢                                      xe2x80x83                                    ⁢                  ω                  ⁢                                      xe2x80x83                                    ⁢                  Lo                                                                              G                  p                                +                                  j                  ⁢                                      xe2x80x83                                    ⁢                  ω                  ⁢                                      xe2x80x83                                    ⁢                  Co                                                              .                                    (        3        )            
Assuming that the conductor resistance per unit length, Rs, and the dielectric conductance per unit length, Gp, are small, the characteristic impedance Zo of the bus signal line segment is approximated by relationship four as follows:                     Zo        =                                            Lo              Co                                .                                    (        4        )            
FIG. 2 also shows the dominant electrical properties at the memory device I/O pins 56-D at nominal operating frequencies. For the memory devices 42, the effective input inductance is LI, the effective input capacitance is CI, and the effective input resistance is RI. The input resistance RI incorporates all input losses including metallic, ohmic, and on-chip substrate losses. The input resistance RI is also directly proportional to the frequency. Assuming that the input capacitance CI dominates, the input electrical characteristics of the memory devices 42 is in accordance with relationships five and six as follows:                               Xc          =                                                    1                                  2                  ⁢                                      xe2x80x83                                    ⁢                  π                  ⁢                                      xe2x80x83                                    ⁢                                      fC                    1                                                              ⪢                              X                L                                      =                          2              ⁢                              xe2x80x83                            ⁢              π              ⁢                              xe2x80x83                            ⁢                              fL                1                                                    ,        and                            (        5        )                                Xc        =                              1                          2              ⁢                              xe2x80x83                            ⁢              π              ⁢                              xe2x80x83                            ⁢                              fC                1                                              ⪢                                    R              1                        .                                              (        6        )            
At the system operating frequency, the effective loaded impedance, ZL, of the bus signal lines 54 is closely approximated in accordance with relationship seven as follows:                               Z          L                =                                                                              L                  o                                ·                d                                                              (                                                            C                      o                                        ·                    d                                    )                                +                                  C                  1                                                              .                                    (        7        )            
The lumped capacitance CI at the memory devices I/O pins 56-D is distributed into the bus signal line segments 64 and into the effective impedance of the transmission lines to change the effective impedance of the structure from the higher unloaded value of Zo to a lower, loaded impedance of ZL. This is possible as long as the electrical length d of the bus signal line segments 64 is less than the rise and/or fall times of the signals on the data bus 46. If the electrical length d of the segments 64 is too long, the bus signal line 54 will look like a series of transmission lines 64 having impedance Zo with capacitive loads of magnitude CI placed at intervals of length d, rather than appearing to distribute the lumped capacitance CI into the bus signal line 54. By choosing an appropriate inductance per unit length of Lo, capacitance per unit length of Co, and electrical length d for the segments 64, the bus signal line 54 can provide a continuous impedance at a desirable effective loaded impedance ZL despite the lumped parasitic input capacitances CI at the memory devices"" I/O pins 56-D. Typically, practical considerations, such as manufacturing tolerances, limit the characteristic impedance Zo to less than seventy-five ohms.
A periodic-bus signal line structure having a loaded impedance ZL using segments 64 of impedance Zo and length d between the memory devices 42 produces a bus signal line 54 that has a total length equal to at least the product of the segment length d and the number of memory devices 42. If needed, the total length of the bus signal line 54 can be increased by attaching transmission lines having a characteristic impedance equal to the loaded impedance ZL, (i.e., ZO=ZL) to either one or both ends of the periodic signal line structure. However, the total length of the bus signal line 54, and therefore the number of memory devices 42, is limited by timing considerations. Therefore, a memory system that increases the number of memory devices attached to a memory system is needed.
The periodic structure is formed by connecting each memory device 42 to an adjacent memory device at a regular spacing, which is called the pitch. A typical pitch is equal to approximately ten millimeters (mm). The periodic structure has a bandwidth (passband), and a loaded bus impedance (Bloch impedance). Decreasing the pitch of the periodic structure increases the passband and reduces the Bloch impedance. However, the minimum amount of pitch is limited by the physical size of the memory device 42 and board layout requirements. Therefore, an apparatus and method that increases the passband and reduces the Bloch impedance while meeting the pitch requirements is needed.
The repetitive arrangement of the memory devices 42 at intervals of length d along the bus signal line 54 also causes the bus signal line 54 to act as a multi-pole low-pass filter. Because the impedance characteristics of the loaded, terminated bus signal lines 54 provide frequency-dependent propagation paths for signals transmitted between the master device 44 and the memory devices 42, the bus signal lines 54 may also be referred to as propagation channels.
In FIG. 3, the frequency response (H(f)) for bus signal lines having four, eight and sixteen memory devices at a given loaded impedance ZL and input capacitance CI is shown. The cut-off frequency of a bus signal line, and therefore the bandwidth, decreases as the number (N) of memory devices 42 increases. Referring also to FIG. 2, each memory device 42 acts like a lossy load that attenuates a signal. The lossy nature of the load from the memory device 42 decreases the passband as the number of memory devices increases because of the attenuation of the memory devices 42. An attenuation of 1.5% per memory device 42 is typical and results in a loss of signal amplitude of about 50% when thirty-two memory devices 42 are attached to a signal line. The attenuation places a practical limit on the number of memory devices 42 that can be attached to a bus signal line because decreasing the passband reduces system performance.
In FIG. 4, the frequency response (H(f)) for bus signal lines having memory devices spaced at three different distances at a given loaded impedance ZL and input capacitance CI is shown. The relationships between the distances (d1, d2 and d3) between adjacent memory devices are in accordance with relationship eight as follows:
d1 less than d2 less than d3.xe2x80x83xe2x80x83(8)
The cut-off frequency of the bus signal line response (H(f)), and therefore the bandwidth, decreases as the distance between the memory devices 42 increases. Since the minimum distance between adjacent memory devices 42 is limited by practical space considerations and since the bandwidth decreases as the number of memory devices 42 increases, the memory system 50 is limited in both bandwidth and capacity. To maintain a desired loaded impedance and bandwidth while increasing the number of memory devices 42, the bus signal line structure is changed in two ways. First, the distance d (64FIG. 2) between adjacent memory devices 42 is decreased to compensate for the reduction in bandwidth because the number of memory devices 42 attached to the bus signal line 54 has increased.
Second, the characteristic impedance, Zo, of the segments 64 (FIG. 2) is increased to maintain the desired loaded impedance ZL while distributing the memory device input capacitance CI across the shortened signal line segments 64 (FIG. 2). However, there is a practical limit to the distance d between adjacent memory devices; and the characteristic impedance of the memory device is typically limited to below seventy-five ohms. Consequently, the maximum allowable number (N) of memory devices 42 in the system 50, and therefore the system memory capacity, is limited. This capacity limitation is a problem for systems requiring a memory system with both high bandwidth and a large capacity. Therefore an expandable memory system that provides high bandwidth and a large capacity is needed.
Decreasing the pitch between the memory devices 42 decreases the loaded bus impedance of the signal lines 54. For a predefined voltage swing, as the pitch is reduced, more power is needed to drive the signal lines 54 of the bus with that voltage swing. A predefined voltage swing is necessary for proper receiver operation. A typical voltage swing is equal to approximately 800 millivolts (mV); and, a typical loaded bus impedance is equal to approximately thirty ohms. To drive a signal line 54 in one direction, the drive circuit of the master device 42 sinks approximately twenty-six milliamperes (mA) of current. To drive a signal line in two directions with a limitation of sinking twenty-six mA of current, a drive circuit of a memory device 42 will transmit a 400 mV signal, not an 800 mV signal, towards both the resistive terminator and the master device. A reflection restores the 400 mV signal to its full size. Because drive circuits are limited as to the amount of current they can sink, it is not desirable to increase the size of the transistors of the drive circuit.
Referring back to FIG. 2, transmission lines with loads spaced at a constant pitch can be analyzed as periodic structures. The signal line 54 is a type of transmission line and the loads are the memory devices 42. The signal line 54 operates in accordance with relationship nine as follows:                                           cos            ⁡                          (              bd              )                                =                                    cos              ⁡                              (                kod                )                                      -                                                            (                                      Zo                                          2                      ⁢                      Y                                                        )                                ·                sin                            ⁢                              xe2x80x83                            ⁢                              (                kod                )                                                    ,                            (        9        )            
The propagation constant for the loaded signal line is b. The unloaded propagation constant is ko. The pitch of the memory devices 42 is d. The unloaded impedance of the signal line is Zo. The admittance of each memory device 42 is Y. Relationship nine can be solved for bd, where b is the quotient of the radian frequency w of the wave on the signal line and the propagation velocity vp, i.e., b=w/vp.
The following information can be discerned from relationship nine, called a dispersion relation. First, for a given unloaded propagation constant b and given memory device load, decreasing the pitch reduces the passband, and therefore performance. Increasing the number of memory devices 42 while maintaining the same pitch does not affect the passband of the loaded signal line. Second, for a given unloaded propagation constant, a given memory device load and a given pitch, the passband is defined by the maximum value for b called b_max. For example, a signal line with an unloaded propagation constant ko equal to fifty-two, with a load of two picofarads (pf) and a pitch of seven mm on a thirty ohm signal line, the passband maximum velocity b_max is equal to approximately 100 radians/meter. At a frequency of 1.2 gigahertz (GHz), the loaded propagation velocity of the signal line 54 is approximately equal to 0.25 c, where c is equal to the speed of light. If the pitch is increased to fourteen mm, the passband maximum velocity b_max increases to equal approximately 200 radians/meter. Maintaining a constant propagation velocity, the passband frequency increases to about 2.4 GHz. Thus, doubling the pitch between memory devices 42 doubles the frequency of the passband. Assuming a constant propagation velocity, the passband frequency increases to allow for more throughput on the signal line 54. Third, there is tradeoff between the number of memory devices 42 attached to the signal line 54 and the total length of the signal line 54. Increasing the number of memory devices 42 while maintaining a constant length decreases the pitch, and therefore decreases the passband. The passband is directly proportional to the data rate. Therefore the capacity and data rate of a memory system are inversely related to each other. Furthermore, when increasing the capacity of the system, the lossy load of the memory devices 42 increases the attenuation on the signal line. The increased attenuation limits the number of memory devices 42 on the signal line 54 regardless of the pitch and further reduces the passband. Therefore, a memory system is needed that maintains or increases the data rate while increasing the capacity.
Another limitation of the prior art memory system 50 of FIG. 1 is the read-write bubble problem which decreases bus utilization efficiency. A read-write bubble is a an interval of time during which the master device must remain idle and cannot read or write data. The read-write bubble results when a write to a closer memory device on the bus immediately precedes a read from a more distant memory device on the bus. The more distant memory device waits to transmit its read data so that it will not interfere with the reception of the write data at the closer memory device. The read-write bubbles reduce the bus utilization efficiency from an ideal of 100%. In addition, read-write bubbles increase the latency when reading data because the more distant memory device waits before transmitting data. Therefore, a memory system that reduces the latency, or read/write bubbles, is needed.
A bus system for use with addressable slave devices has a global bus of uni-directional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus. First and second global bus terminators are coupled to the first and second ends of the global bus, respectively. One or more subsystems are connected in parallel with each other and to the master device via the global bus. Each subsystem includes a local bus, one or more slave devices coupled to the local bus, a write buffer that receives incoming signals from the master device via the global bus and transmits the incoming signals to the one or more slave devices via the local bus, and a read buffer that receives outgoing signals from the one or more slave devices via the local bus and transmits the outgoing signals to the master device via the global bus.
In one embodiment, the slave devices include memories. In another embodiment, the subsystem includes first and second subsystem terminators that are coupled to the local bus. In yet another alternate embodiment, at least one of the first and second subsystem terminators is an active terminator.